Partcl GTM brain

Partcl sells GPU-accelerated chip design automation software to semiconductor engineering teams.

category

Chip design automation

market profile

  • text: Physical design teams face slow placement, routing and timing feedback that limits design exploration.
  • text: Incumbent EDA tooling is deeply embedded in chip flows, raising the cost of switching.

personas

  • title: Director of physical design
    pains:
    • Long implementation iterations constrain timing closure and tapeout schedules
    • A new flow must demonstrate comparable quality on actual design blocks
  • title: RTL design engineer
    pains:
    • Slow physical feedback makes it hard to evaluate RTL changes
    • Power, performance and area tradeoffs require many experiments
  • title: VP of silicon engineering
    pains:
    • Expensive engineering cycles delay silicon delivery
    • New EDA infrastructure must justify adoption and compute costs

icp

  • text: Fabless semiconductor and custom silicon teams performing physical implementation and timing analysis; company size is unspecified.
  • text: Teams with GPU compute and recurring RTL or physical design iterations are plausible early adopters.

message pillars

  • text: Accelerate EDA with GPUs.
  • text: Support physical design workflows.
  • text: Build for the chip designer.

objections

  • objection: We cannot risk our established flow near tapeout.
    response: Run a side-by-side evaluation on a representative block and compare timing, area and output quality before migration.
  • objection: GPU infrastructure and integration may outweigh speed gains.
    response: Benchmark elapsed time and total compute cost on the actual workload before committing.

competitors

  • name: ChipAgents
    why: AI-assisted chip design and verification tooling overlaps the design workflow.
  • name: Silimate
    why: Chip design analysis and optimization competes for design engineers' workflows.
  • name: Synopsys
    why: Established EDA vendor with physical design tools.
  • name: Cadence
    why: Established physical design and timing software provider.

influencers

  • name: William Salcedo
    url: https://www.linkedin.com/in/william-salcedo
    why: Founder and CEO shares chip design benchmarks and technical updates.

keywords

  • GPU accelerated EDA
  • chip physical design automation
  • static timing analysis software
  • RTL optimization
  • chip placement and routing
  • EDA design space exploration

voice

  • technical
  • performance-focused
  • concise

signals

  • text: A silicon team is expanding physical design capacity or reporting timing closure delays.
  • text: A design organization is investing in GPUs to speed chip design workloads.

stack

  • GPU

pricing

model: unknown

motion

sales_led

channels

  • LinkedIn
  • technical competitions
  • YC directory

confidence

medium

Founders

  • name: William Salcedo
    title: Founder/CEO
    role: CEO
    bio: CEO at Partcl. Previously at Nvidia, Stanford, and Cornell. I taped-out two chips from scratch as an undergrad and developed one of the earliest chips designed by LLMs. My research at Stanford included using AI techniques to verify circuits.
  • name: Vamshi Balanaga
    title: Founder/CTO
    role: CTO
    bio: CTO at Partcl. Previously built embedded ML models at Apple, laser weeding robots at Carbon Robotics, and warehouse automation robots at Fulfil Solutions. Built and launched multiple rockets while running the avionics team at Space Enterprise at Berkeley, Stanford EECS PhD (dropout), UC Berkeley Physics.

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